Drone FPGA Radio-Telescope Beam Mapping

We will fly a large hexacopter drone with a weak radio transmitter to calibrate the beam pattern of a radio telescope. Our on-campus “telescope” will be a dish antenna on an amateur astronomy telescope mount that can bring outside and point it in different direction to map out its beam pattern.

We transmit a custom wide-band signal out of a fast FPGA-controlled digital to analog converter (DAC) with 16-bit samples at 4 GHz. We receive the signal with an equally-fast analog to digital converter (ADC). We perform digital signal processing (DSP) with Fast Fourier Transforms (FFTs) to compare how much of the transmitted signal. This basically makes our own software defined radio (SDR).

I have written custom Verilog code that interfaces with python to transmit and receive fixed-length arrays. Pieces of the project you'd work on include: 

• Working with the FPGA to send samples out of a GHz digital-to-analog converter (DAC) and retrieve samples from a GHz analog-to-digital converter (ADC), store them and analyze them (python, numpy, scipy, jupyter-lab, matplotlib, bokeh).
• Radio frequency (RF) work with amplifiers and antennas.
• Programming flight paths of the drone and analyzing the data that comes out (python, ardupilot, PX4).
• Synchronizing the radio samples with the drone GPS and orientation data (linux, networking).
• Design and build a mount for the antenna and transmitter on the drone, along with a mount for our test "radio telescope" antenna on the ground. (Laser cutter, 3D printing).
• Making the electrical system of the drone and radio robust and reliable on battery power (Circuits and soldering).

Please list your relevant experience, detailing your particular contribution to any group projects. Relevant skills include the above, but also any of:

• All software is numpy-based python running on Linux, so experience in Linux, especially with things like low-level networking and serial ports would be relevant.
• C or C++ array and pointer management at the level of CS70
• Computer architecture at the level of E85
• Digital signal processing at the level of E101

Not all of this background is required, but to accept any ambitious 1st or 2nd year students, I'd need to be convinced of your ability to independently pick up a useful subset.

Two or three students will participate. You must be willing to commit 4, 8, or 12 hours/week on this project in the spring in 3-4 hour blocks. There will be a separate application later for summer, funding pending, which would require committing to 10 weeks, usually starting the first or second week.