RISC-V Microprocessor Verification and Design

Harvey Mudd College has become a major developer of the configurable, open CORE-V Wally microprocessor and of the RISC-V Certification test plan and suite.  The Clay-Wolkin Fellowship is supported by RISC-V International and Qualcomm in these efforts, and collaborates with companies around the world including Synopsys, Breker, Tenstorrent, and 10x Engineers.

The Clay-Wolkin Fellowship  will have openings for Spring 2026 at Prof. Harris's Very Large Scale Integration (VLSI) Design Lab.  The most common time to join is as a sophomore, especially if taking E154 RISC-V System-on-Chip Design, but juniors and frosh with exceptional backgrounds will also be considered. CS and Engineering students are most common, but unusual students from other majors have done excellent work in the group in the past. Prospective fellows will start on a volunteer basis in the spring, and those who find they love the research and are contributing effectively may join the Fellowship.  Most Clay-Wolkin fellows continue research through each academic year at HMC, and some stay for one or more summers of research, while others choose summer internships.

Areas of interest include:

• RISC-V Certification: development of tests plans, test generators, and automation to certify RISC-V microprocessors.  This work will be released open-source by RISC-V International.
• RISC-V Verification: developing tests for new features such as on-chip Debug.
• RISC-V Design: adding new features to CORE-V Wally, including on-chip debug and RVA23 Profile features.

Priority for new fellows in Spring 2026 specifically includes focuses on RISC-V certification and bringing CORE-V Wally to Technology Readiness Level 5, collaborating with experienced Clay-Wolkin Fellows:

• Improving privileged test generators for RISC-V certification to directly relate individual tests to coverpoints and normative rules.  This will involve developing a strong understanding of the RISC-V specification, writing test generators in Python that produce RISC-V assembly language, and debugging the tests using instruction-set simulation and SystemVerilog simulation. Tests should achieve 100% functional coverage on all features supported by CORE-V Wally.
• Contributing to the certification framework to automate running certification tests.  This will involve a strong understanding of the RISC-V specification and may involve working with Python, Makefiles, and/or shell scripts.
• Developing floating-point functional coverage models in SystemVerilog and tests.  This will involve a deep understanding of IEEE Floating-Point, writing coverpoints in SystemVerilog, writing test generators in Python, debugging interactions with the C-based SoftFloat reference model, debugging coverage, and creating RISC-V assembly language tests.  A strong interest in floating-point math is helpful, especially related to subtle issues of inexact mathematics.
• Developing new coverpoints and tests for additional features in the RVA23 application processor specification, including the RISC-V Debug Specification.
• Developing code coverage tests to bring the CORE-V Wally SystemVerilog code to Technology Readiness Level 5. This will involve analyzing code coverage reports and developing RISC-V assembly language tests to exercise features with missing coverage, applying waivers to features that should not be covered, or adjusting the SystemVerilog code to be cleaner and easier to cover.